Buses

In ARM Cortex-M microcontrollers, buses are internal pathways that allow communication between the CPU core, memory (Flash and RAM), and peripherals. Unlike general-purpose computers that may have a single system bus, Cortex-M microcontrollers usually implement a bus matrix or interconnect to achieve parallelism and efficiency.

These buses follow the AMBA (Advanced Microcontroller Bus Architecture) specification, which defines several types of buses used in microcontroller system design. These buses differ based on their function, target, and performance.

1. Overview of Bus Types

The primary internal buses in Cortex-M cores (like M3, M4, and M7) include:

1. I-Code Bus: Used for fetching instructions from Flash memory. It is read-only and optimized for fast instruction access.
2. D-Code Bus: Used for reading or writing data in the Flash memory. This supports literal constants and lookup tables in the code space.
3. System Bus: A general-purpose bus for accessing RAM, peripherals, and system components.

All of these buses are implemented using the AHB-Lite interface, a simplified version of AMBA AHB designed for single-master systems like Cortex-M.

2. Functional Classification

• I-Code and D-Code Buses enable parallel access to Flash memory, improving instruction throughput and execution efficiency. (Hints to Modified Harvard Architecture: Modified Harvard Architecture)

• The System Bus connects the processor to data memory (SRAM) and peripheral registers and is also shared with other system components like DMA.

3. Additional Buses

• Private Peripheral Bus (PPB): Connects to core system components such as the NVIC, SysTick, and debugging units. This is internal to the processor and mapped to a fixed address region (0xE0000000).

• Advanced Peripheral Bus (APB): A slower, simpler bus used for connecting low-speed peripherals like UARTs, GPIOs, and timers. It is accessed via an AHB-to-APB bridge.

• Tightly Coupled Memory (TCM) Buses – used for deterministic access to RAM (e.g. in Cortex-M7)

4. Bus Differences in Cortex-M Variants

• Cortex-M0/M0+: These cores have a single unified AHB-Lite System Bus without separate I-Code and D-Code buses.

• Cortex-M3/M4/M7: These support multiple buses (I-Code, D-Code, System) to allow instruction and data access in parallel, improving performance.

• Cortex-M7 and above may include a bus matrix that allows multiple masters (like CPU, DMA) to access different memory regions simultaneously.

5. Summary Table

Bus	Used For	Access Type	Typical Target
I-Code	Instruction fetch	Read-only	Flash
D-Code	Data access in Flash	Read/Write	Flash
System	RAM and peripherals	Read/Write	SRAM, peripherals
PPB	System registers	Read/Write	NVIC, debug units
APB	Low-speed peripherals	Read/Write	UART, GPIO, etc.